1. Field of the Invention
Embodiments of the invention relate to circuits, and in particular, to clock and data recovery circuits.
2. Description of the Related Art
In transmitting electronic data from one component to another, a clock is typically used for timing processing the electronic data. In some applications, a clock signal is transmitted along with electronic data from a transmitting component to a receiving component. In other applications, no clock signal is transmitted from a transmitting component to a receiving component. Instead, a clock is derived at the receiving component from electronic data from the transmitting component. Such a scheme is generally referred to as clock and data recovery (CDR).
FIG. 1 illustrates a conventional receiver 100 for receiving electronic data, using a clock and data recovery scheme. The receiver 100 includes an equalizer 110, one or more buffers 120 and a clock and data recovery (CDR) circuit 130. The receiver 100 receives data via a channel from a transmitting component (not shown), but does not receive a separate clock signal.
FIG. 2 illustrates the architecture of a conventional CDR circuit 200. The CDR circuit 200 includes a data sampler 210, an edge sampler 220, a phase detector 230, a phase filter 240, and a phase picker 250. The data sampler 210 and the edge sampler 220 can each include a sampling circuit (sampling the bit stream at a particular time) and a slicer to convert the bit stream to −1 and +1 or to 0 and 1. These components 210-250 together form a CDR feedback loop. The data sampler 210 and the edge sampler 220 provide data samples and edge samples, respectively, to the phase detector 230. The phase detector 230 provides an UP signal and a DOWN signal to the phase filter 240. The phase filter 240 provides a phase selection code to the phase picker 250. The phase picker 250 provides a data clock signal and an edge clock signal to the data sampler 210 and the edge sampler 220, respectively.
The CDR circuit 200 uses a number of clock phases to sample an incoming data signal. FIG. 3 is an example eye diagram 300 for a digital data signal. The eye diagram 300 is a composite of many measurements taken upon separate instances of the incoming signal. The CDR circuit 200 of FIG. 2 samples the incoming data signal at both the midpoints and edges of data eyes (i.e., data valid intervals). The data sampler 210 obtains data samples ( . . . Dn−2, Dn−1, Dn, Dn+1, Dn+2, . . . ) and the edge sampler 220 obtains edge samples ( . . . En−2, En−1, En, En+1, En+2, . . . ), respectively. If the data samples that bound a given edge sample indicate a transition between high and low states, then the edge sample indicates whether the clock edge used to trigger the edge sampling operation occurred early or late relative to the data signal transition, and therefore may be used to adjust the clock phase.
Referring to expanded view 310, for example, data samples Dn−1 and Dn are logic “0” and “1” values, respectively, and therefore indicate a rising-edge transition in the incoming data signal. If the edge-sampling clock edge is early relative to the data signal transition, the edge sample will be captured before the data signal crosses decision threshold, DT (i.e., the threshold compared with the incoming signal to resolve the logic state of the edge and data samples), and therefore will have a logic-low (“0”) state. If the clock edge is late relative to the data signal transition, the edge sample, Tn will have a logic-high (“1”) state. Conversely, in a falling-edge transition of the data signal, a logic “1” edge sample indicates an early clock edge, and a logic “0” edge sample indicates a late clock edge.
Referring back to FIG. 2, these data and edge samples are interpreted by the phase detector 230 which decides if the clock phases are early or late with respect to the data signal. The outcome of this decision is contained in the UP/DOWN signals forwarded from the phase detector 230 to the phase filter 240. The phase filter 240 further processes this information and provides the phase selection code to the phase picker 250. The phase picker 250 uses the selection code to pick which phases out of a number of available phases that will be sent to the samplers 210, 220 to sample the data.
The phase picker 250 provides the data clock signal to the data sampler 210, and the edge clock signal to the edge sampler 220. The data sampler 210 uses the data clock signal for timing the acquisition of data samples from the middle of an eye in an eye diagram (e.g., the eye diagram of FIG. 3). The edge sampler 220 uses the edge clock signal for timing the acquisition of edge samples from the edge of the eye.
By this operation, the phase of the edge clock signal is iteratively adjusted to achieve and maintain alignment between transitions of the edge clock signal and edges of the data eyes. The data clock signal (i.e., the clock signal used to trigger data sampling operations) is phase offset from the edge clock signal such that data clock transitions are evenly spaced in time between leading and trailing edge clock transitions, thereby establishing the data sampling point at the midpoint between edges of the data eyes.
The data samples represent the recovered data and are sent to the output of the CDR circuit 200. Edge samples are not sent to the output of the CDR circuit 200. Both the data and the edge samples are used internally by the CDR circuit 200 to extract phase alignment information as set forth above.